TY - JOUR
T1 - VLSI architectures for multidimensional transforms
JF - Computers, IEEE Transactions on
Y1 - 1991
A1 - Chakrabarti,C.
A1 - JaJa, Joseph F.
KW - architecture;
KW - architectures;
KW - arithmetic;
KW - complexity;
KW - computational
KW - Computer
KW - digital
KW - fixed-precision
KW - linear
KW - multidimensional
KW - separable
KW - transforms;
KW - VLSI
AB - The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N times;N times; . . . times;N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(N^{d+2a}) and computation time T=O(dN^{d/2-a}b ), and achieve the AT^{2} bound of AT^{2}=O(n^{2}b ^{2}) for constant d, where n=N^{d } and O lt;a les;d/2
VL - 40
SN - 0018-9340
CP - 9
M3 - 10.1109/12.83648
ER -