%0 Journal Article
%J IEEE Transactions on Signal Processing
%D 2006
%T Contention-conscious transaction ordering in multiprocessor DSP systems
%A Khandelia,M.
%A Bambha,N. K
%A Bhattacharyya, Shuvra S.
%K contention-conscious transaction ordering
%K Costs
%K data flow graphs
%K Dataflow
%K Delay
%K Digital signal processing
%K digital signal processing chips
%K Embedded system
%K graph-theoretic analysis
%K Instruments
%K Internet telephony
%K interprocessor communication
%K iterative dataflow graphs
%K iterative methods
%K Message passing
%K multiprocessor
%K multiprocessor DSP systems
%K NP-complete problem
%K Processor scheduling
%K scheduling
%K Signal processing
%K synchronization
%K Throughput
%X This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.
%B IEEE Transactions on Signal Processing
%V 54
%P 556 - 569
%8 2006/02//
%@ 1053-587X
%G eng
%N 2
%R 10.1109/TSP.2005.861074