%0 Conference Paper
%B Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
%D 2005
%T Algorithmic and architectural design methodology for particle filters in hardware
%A Sankaranarayanan,A. C
%A Chellapa, Rama
%A Srivastava, A.
%K (numerical
%K algorithmic
%K architectural
%K architectures;
%K bearing
%K complexity;
%K computational
%K design
%K digital
%K evolution;
%K Filtering
%K filtering;
%K filters;
%K implementation;
%K methodology;
%K methods);
%K nonGaussian
%K nonlinear
%K only
%K Parallel
%K particle
%K pipeline
%K pipelined
%K problem;
%K processing;
%K state
%K tracking
%K VLSI
%K VLSI;
%X In this paper, we present algorithmic and architectural methodology for building particle filters in hardware. Particle filtering is a new paradigm for filtering in presence of nonGaussian nonlinear state evolution and observation models. This technique has found wide-spread application in tracking, navigation, detection problems especially in a sensing environment. So far most particle filtering implementations are not lucrative for real time problems due to excessive computational complexity involved. In this paper, we re-derive the particle filtering theory to make it more amenable to simplified VLSI implementations. Furthermore, we present and analyze pipelined architectural methodology for designing these computational blocks. Finally, we present an application using the bearing only tracking problem and evaluate the proposed architecture and algorithmic methodology.
%B Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
%P 275 - 280
%8 2005/10//
%G eng
%R 10.1109/ICCD.2005.20