%0 Conference Paper
%B Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
%D 2004
%T Arbitrate-and-move primitives for high throughput on-chip interconnection networks
%A Balkan,A.O.
%A Gang Qu
%A Vishkin, Uzi
%K 8
%K arbiter
%K arbitrate-and-move
%K architecture;
%K asynchronous
%K balanced
%K binary
%K circuit
%K circuit;
%K circuits;
%K consumption;
%K data
%K explicit
%K interconnection
%K interconnections;
%K leaf
%K mesh-of-trees
%K multi-threading;
%K Multithreading
%K n-leaf
%K network;
%K pipeline
%K pipelined
%K power
%K primitive
%K processing;
%K reduced
%K simulation;
%K structures;
%K synchronous
%K synchrony
%K system-on-chip;
%K tree
%K tree;
%X An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.
%B Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
%V 2
%P II - 441-4 Vol.2 - II - 441-4 Vol.2
%8 2004/05//
%G eng
%R 10.1109/ISCAS.2004.1329303