%0 Conference Paper
%B 2010 International Conference on Embedded Computer Systems (SAMOS)
%D 2010
%T Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs
%A Kee, Hojin
%A Bhattacharyya, Shuvra S.
%A Kornerup, J.
%K buffer memory
%K circuit complexity
%K Complexity theory
%K Computational modeling
%K data flow graphs
%K Digital signal processing
%K digital signal processing chips
%K DSP system design
%K efficient static buffering
%K Field programmable gate arrays
%K FPGA
%K graph buffer distributions
%K integrated circuit design
%K low polynomial time complexity
%K Random access memory
%K Schedules
%K SDF graph edges
%K Signal processing systems
%K Synchronous dataflow
%K synchronous dataflow graph mapping
%K Throughput
%K throughput-optimal execution
%K throughput-optimal FPGA implementation
%K two-actor SDF graph model
%K upper bounds
%X When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flow-graph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed technique is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.
%B 2010 International Conference on Embedded Computer Systems (SAMOS)
%P 136 - 143
%8 2010
%G eng