An extraction-based verification methodology for MEMS

TitleAn extraction-based verification methodology for MEMS
Publication TypeJournal Articles
Year of Publication2002
AuthorsBaidya B, Gupta SK, Mukherjee T
JournalMicroelectromechanical Systems, Journal of
Pagination2 - 11
Date Published2002/02//
ISBN Number1057-7157
Keywordsatomic level, canonical representation, circuit schematic representation, circuit simulation, design cycles, design productivity, design verification, digital simulation, equivalent circuits, equivalent microelectromechanical circuit, extraction-based verification methodology, feature-based recognition algorithms, functional behavior, functional level, graph-based recognition algorithms, layout extraction, lumped parameter networks, lumped-parameter circuit simulation, MEMS, microelectromechanical circuit simulators, micromachining techniques, micromechanical devices, simulation accuracy, simulation time

Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity