System-level Clustering and Timing Analysis for GALS-based Dataflow Architectures

TitleSystem-level Clustering and Timing Analysis for GALS-based Dataflow Architectures
Publication TypeConference Papers
Year of Publication2009
AuthorsShen C, Bhattacharyya SS
Conference NameIn Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, Texas, February 2009.
Date Published2009///

In this paper, we propose an approach based ondataflow techniques for modeling application-specific, globally
asynchronous, locally synchronous (GALS) architectures for
digital signal processing (DSP) applications, and analyzing the
performance of such architectures. Dataflow-based techniques
are attractive for DSP applications because they allow applica-
tion behavior to be represented formally, analyzed at a high
level of abstraction, and synthesized to software/hardware
implementations through an optimized, automated process. In
our proposed methodology, we employ dataflow-based compu-
tational models to expose relevant structure in the targeted
applications, and facilitate the manual or automatic derivation
of efficient implementations. We demonstrate the utility of our
modeling and analysis techniques by applying them as core
parts of a novel clustering algorithm that is geared towards
optimizing the throughput of GALS-based DSP architectures.