Systematic exploitation of data parallelism in hardware synthesis of DSP applications

TitleSystematic exploitation of data parallelism in hardware synthesis of DSP applications
Publication TypeConference Papers
Year of Publication2004
AuthorsSen M, Bhattacharyya SS
Conference NameAcoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on
Date Published2004/05//
Keywordsarea-performance trade-off curve, automatic Verilog code generation, circuit optimisation, data flow graphs, data parallelism, dedicated hardware implementation synthesis, design tool, Digital signal processing, DSP applications, embedded systems, hardware description languages, hardware synthesis, high level synthesis, high level synthesis algorithm, IMAGE PROCESSING, PARALLEL PROCESSING, power consumption, Signal processing, synchronous dataflow graph, video processing

We describe an approach that we have explored for low-power synthesis and optimization of image, video, and digital signal processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in a dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and, based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit.